Flip-flop circuit

ABSTRACT

A flip-flop circuit comprising: a first, a second, a third, a fourth, a fifth, a sixth, and a seventh field effect transistor; wherein a first pulse signal is applied to the input electrode of said third field effect transistor, a second pulse signal substantially synchronized with said first pulse signal is applied to the input electrode of one of said fifth and sixth field effect transistors and to the input electrode of said fourth field effect transistor, an input signal is applied to the input electrode of the other of said fifth and sixth field effect transistors, and a third pulse signal having its phase different from that of said first pulse signal is applied to the input electrode of said seventh field effect transistor.

United States Patent Nomiya et al.

[ Oct. 29, 1974 3,697,775 [0/1972 Kane 307/279 X Primary ExaminerJohn S. Heyman Attorney, Agent, or FirmCraig & Antonelli [57] ABSTRACT A flip-flop circuit comprising: a first, a second, a third, a fourth, a fifth, a sixth, and a seventh field effect transistor; wherein a first pulse signal is applied to the input electrode of said third field effect transistor, a second pulse signal substantially synchronized with said first pulse signal is applied to the input electrode of one of said fifth and sixth field effect transistors and to the input electrode of said fourth field effect transistor, an input signal is applied to the input electrode of the other of said fifth and sixth field effect transistors, and a third pulse signal having its phase different from that of said first pulse signal is applied to the input electrode of said seventh field effect transistor,

8 Claims, 9 Drawing Figures l l FLIP-FLOP CIRCUIT I76] Inventors: Kosei Nomiya, 2-47-l6 Eifuku,

Suginami-ku, Tokyo; Hiroto Kawagoe, l2l l Gakuennishi-machi, Tokyo, both of Japan [22] Filed: Mar. 27, 1973 I21] Appl. No.: 345,474

[30] Foreign Application Priority Data Mar. 27, I972 Japan t, 47-29729 I52] U.S. Cl. 307/279, 307/247 R [5 ll Int. Cl. H03k 3/286 [58] Field of Search 307/279, 247 R [56] References Cited UNITED STATES PATENTS 3 (1l(l,964 l(l/l97l Hatano .7 307/279 H4 il Ti? Tu: We H4 BACKGROUND OF THE INVENTION l. Field of the Invention The present invention relates to flip-flop circuits and more particularly to static flip-flop circuits using field effect transistors.

2. Description of the Prior Art Flip-flop circuits comprised of insulated gate field effect transistors may be classified broadly as dynamic flip-flop circuits and static flip-flop circuits. The former type is simpler in construction than the latter but in some cases the latter is more desirable than the former with respect to data-holding ability.

FIG. 1 illustrates an example of a static flip-flop circuit comprised of field effect transistors. More specifically, this flip-flop circuit consists essentially of a first inverter circuit comprising transistors T, and T a second inverter circuit comprising transistors T and T a third inverter circuit comprising transistors T and T and transistors T T and T which are to serve for transfer gate purposes. The second and third inverter circuits are connected in cascade, and the output terminal of the third inverter circuit is connected to the input terminal of the second inverter circuit by way of the transfer gate transistor T thereby forming a feedback loop where data is held. The contents of data held in the feedback loop depend on the output state of the first inverter circuit when the transfer gate transistor T turns on. The transistors T and T receive at their gate electrodes a clock signal (1) and the transistor T at its gate electrode a clock control signal 4),, with a phase different from that of the clock signal (1) The load transistors T T and T receive at their drain electrodes a DC power supply V and at their gate electrodes a DC power supply V having a voltage higher than that of the DC power supply V by about the threshold voltage of the transistor.

In this circuit. the voltage applied to the gate electrodes of the transfer gate transistors T T and T must stand as high a level (eg, the same level as V as that applied to the load transistors T T and T because of the known substrate effect. Hence, in the prior art, the clock pulse signal (b has been provided at a high voltage level by the use of suitable means such as an astable multivibrator outside the semiconductor integrated circuit device.

The clock control signal (1),, is provided through a logic operation taken between a clock signal (1), (not used in the circuit of FIG. I). which is generated by an astable multivibrator or the like, at a high voltage and has a phase different from the clock signal (11 and an other pulse signal. This logic operation is performed in a logic circuit associated with the semiconductor integrated circuit in which the flip-flop circuit is formedv The logic output stands at nearly the same potential or as low a potential as the DC power supply V Gener ally, therefore. le cl conversion is required to be carried out outside the semiconductor integrated circuit device in order to raise the logic output voltage whereby a high level clock control signal is formed. One prior art improvement is the use of another power source for the semiconductor integrated circuit device, thereby increasing the output level ofthe logic circuit. This in turn necessitates additional external terminals installed on the integrated circuit device.

SUMMARY OF THE INVENTION An object of the invention is to provide a static flip flop circuit capable of operation with a low level clock control signal.

Other objects, features and advantages of the invention will become apparent from the following descrip tion with reference to the accompanying drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional static flip-flop circuit using MOS transistors;

FIG. 2 is a circuit diagram ofa static flip-flop circuit according to this invention; and

FIGS. 3a-3g are waveform diagrams illustrating operations of the circuit of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 2 there is shown a flip-flop circuit of the invention, wherein the symbol T denotes a transistor connected between a power terminal V and ground by way ofa transistor T which receives a clock signal (1) as its input. T is a transistor having its gate connected to the source electrode of said first transistor T This transistor T is connected between the power terminal V and ground via a transistor T which receives a clock signal 4), as its input. T is a transistor supplied with the clock signal d), at its gate electrode and connected between the gate electrode of transistor T and the source electrode of transistor T T is a transistor having its gate electrode connected to an input terminal IN, and its source electrode con nected to the drain electrode of transistor T T is a transistor having its gate electrode connected to a clock control input terminal IN This transistor T is connected between the drain electrode of transistor T and ground. T is a transistor connected between the source electrode of transistor T and ground and having its gate electrode connected to the input terminal IN. T is a transistor connected between the source electrode of transistor T and an output terminal OUT and supplied with the clock signal ($2. The transistors T through T are ofthe MOS type. The transistors T and T operate as load resistors. The transistors T and T operate as amplifier elements whose gate internal capacity is used for storage purposes. The clock signals d and (b are of a high voltage level generated by an astable multivibrator or the like. The clock control signal d1, is provided through a logic operation between the clock signal da and another pulse signal. Thus, this clock control signal 4), is approximately synchronous with the clock signal (1),. and has nearly the same voltage level as the input signal (lower than (1), and 4J applied to the input terminal IN.,.

This flip-flop circuit operates in the following man ner. Assume that the clock signals (b and (11 as shown in FIGS. 3(a) and 3(b) are supplied to the circuit. When an input signal of FIG. 3(cl is applied to the input terminal IN.,, and a control signal (I), of FIG. 3(d) provided through a logic circuit [not shown) is applied to the input terminal IN the transistor T, turns on in response to the control signal (1),. The transistors T and T perform on/off action synchronously with the clock signal (1),. The transistor T performs onfoff action in response to the input signal. Asa result. the potential at the point a which serves as the gate signal to the transistor T assumes level when the transistors T through T are in the on" state, as shown in FIG. 3(0), or assumes the 1" level when either the input signal or the control signal (I), is zero, i.e., when one of the transistors T and T is in the off" state. The transistor T performs on/off action synchro' nously with the clock signal a. and the transistor T performs on/off action synchronously with the control signal (1),; as a consequence. the potential at the point 1) assumes the l level when only the transistor T is on. or assumes O level when at least one of the transistors T and T is on, as shown in FIG.

The potential at the point b is applied to the gate electrode of transistor T,,,, to operate the transistor T in correspondence to the potential at the point 19 whereby a feedback loop is formed. The transistor T connected between the point b and the output terminal OUT performs on/off action in synchronism with the clock signal As a result, the signal of FIG. 3(3) appears at the output terminal OUT, and the input signal is applied to the output terminal OUT with a delay equal to the phase difference between the clock signals 1b, and d1; only while the control signal (it, is applied. Thus. when the control signal (it is discontinued, this state will remain in storage.

In this operation there is no fear of creating substrate effects because the transistors T and T to which the control signal 4), is supplied have their source electrodes grounded. Therefore, these transistors can easily be driven by the low level control signal (11,. The transistor T is grounded via the transistor T and is operated for reading the input signal only when the transistor T is in the on" state. This means that the source electrode of transistor T is directly grounded when the transistor T is on. Hence, the input signal to the input terminal IN may be of low voltage. This permits the transistor T to be supplied with the control signal (15,, and the transistor T to be supplied with the input signal.

It is apparent that the invention is not limited to this embodiment but various changes and modifications may be made on this embodiment. For example, a DC voltage may be applied to the gate electrodes of the load transistors T and T thus forming a DC drive circuit.

According to the invention, as has been described. there is no fear of causing substrate effects in the MOS transistor to which the clock control signal is supplied, which makes it possible to drive the flip-flop circuit easily and securely by a low level clock control signal.

While there has been shown and described but one embodiment of the invention. it will be understood by those skilled in the art that numerous modifications may be made without departing from the true spirit and scope of the invention as defined in the appended claims.

What is claimed is:

l. A flip-flop circuit comprising: a bias voltage source, a first field effect transistor having its output electrode connected by a first load resistance means to said bias voltage source; a second field effect transistor having its output electrode connected by a second load resistance means to said bias voltage source and its input electrode connected to the output electrode of said first field effect transistor; a third field effect transistor connected between the input electrode of said first field effect transistor and the output electrode of said second field effect transistor; a fourth field effect transistor connected in parallel to said first field effect transistor; a fifth field effect transistor and a sixth field effect transistor connected in series to each other and in parallel to said second field effect transistor; and a seventh field effect transistor connected to the output electrode of said first field effect transistor; first means for applying a first pulse signal to the input electrode of said third field effect transistor, second means for applying a second pulse signal substantially synchronized with said first pulse signal to the input electrode of one of said fifth and sixth field effect transistors and to the input electrode of said fourth field effect transistor, third means for applying an input signal to the input electrode of the other of said fifth and sixth field effect transistors, and fourth means for applying a third pulse signal having its phase different from that of said first pulse signal to the input electrode of said seventh field effect transistor.

2. A flip-flop circuit as defined in claim 1 wherein said first load resistance means is an eighth field effect transistor connected between the output electrode of said first field effect transistor and said bias voltage source.

3. A flip-flop circuit as defined in claim 2 wherein the input electrode of said eighth field effect transistor is connected to said fourth means.

4. A flip-flop circuit as defined in claim 2 wherein a second bias voltage source is connected to the input electrode of said eighth field effect transistor.

5. A flip-flop circuit as defined in claim 2 wherein said second load resistance means is a ninth field effect transistor connected between the output electrode of said second field effect transistor and said bias voltage source.

6. A fiip-flop circuit as defined in claim 5 wherein the input electrode of said ninth field effect transistor is connected to said first means.

7. A flip-flop circuit as defined in claim 5 wherein a second bias voltage source is connected to the input electrode of said ninth field effect transistor.

8. A flip-flop circuit as defined in claim 6 wherein the input electrode of said eighth field effect transistor is connected to said fourth means. 

1. A flip-flop circuit comprising: a bias voltage source, a first field effect transistor having its output electrode connected by a first load resistance means to said bias voltage source; a second field effect transistor having its output electrode connected by a second load resistance means to said bias voltage source and its input electrode connected to the output electrode of said first field effect transistor; a third field effect transistor connected between the input electrode of said first field effect transistor and the output electrode of said second field effect transistor; a fourth field effect transistor connected in parallel to said first field effect transistor; a fifth field effect transistor and a sixth field effect transistor connected in series to each other and in parallel to said second field effect transistor; and a seventh field effect transistor connected to the output electrode of said first field effect transistor; first means for applying a first pulse signal to the input electrode of said third field effect transistor, second means for applying a second pulse signal substantially synchronized with said first pulse signal to the input electrode of one of said fifth and sixth field effect transistors and to the input electrode of said fourth field effect transistor, third means for applying an input signal to the input electrode of the other of said fifth and sixth field effect transistors, and fourth means for applying a third pulse signal having its phase different from that of said first pulse signal to the input electrode of said seventh field effect transistor.
 2. A flip-flop circuit as defined in claim 1 wherein said first load resistance means is an eighth field effect transistor connected between the output electrode of said first field effect transistor and said bias voltage source.
 3. A flip-flop circuit as defined in claim 2 wherein the input electrode of said eighth field effect transistor is connected to said fourth means.
 4. A flip-flop circuit as defined in claim 2 wherein a second bias voltage source is connected to the input electrode of said eighth field effect transistor.
 5. A flip-flop circuit as defined in claim 2 wherein said second load resistance means is a ninth field effect transistor connected between the output electrode of said second field effect transistor and said bias voltage source.
 6. A flip-flop circuit as defined in claim 5 wherein the input electrode of said ninth field effect transistor is connected to said first means.
 7. A flip-flop circuit as defined in claim 5 wherein a second bias voltage source is connected to the input electrode of said ninth field effect transistor.
 8. A flip-flop circuit as defined in claim 6 wherein the input electrode of said eighth field effect transistor is connected to said fourth means. 